Non-volatile memory (NVM), such as electrically erasable programmable read-only memory (EEPROM), flash, etc., are in widespread use in the industry today. Such devices are used in compact flash cards for digital cameras, memory sticks, jump drives, EEPROM chips for booting-up devices (e.g., basic input/output system (BIOS)), and many other applications. Such devices in mass production generally have cells formed by two polysilicon (“poly”) layers, where a first poly layer is used as a floating gate (FG), and a second poly layer is used as a control gate (CG). The control gate may be capacitively coupled to the floating gate using an oxide-nitride-oxide (ONO) layer, which is deposited between the two poly layers. Another type of NVM cell includes a charge storage layer (e.g., a nitride) that is sandwiched between two oxide layers under a poly gate.
Non-volatile cells and latches can be used to store information even when integrated circuit (IC) (“chip”) power is off. In some applications, a non-volatile latch may be a better choice than a single NVM cell because of additional margin in maintaining a stored state. For example, non-volatile latches are used in applications, such as in configuration bits for device configuration state, encryption bits for security, and in any other suitably critical application. The latches may generally be programmed either at a semiconductor device manufacturing site, or in the field.
Many conventional latches are based on a static random-access memory (SRAM) type structure. FIG. 1 shows a conventional back-to-back inverter structure 100 found in an SRAM-type latch. VDD is a power supply coupled to PMOS transistors 106 and 108, while VSS is a ground supply coupled to NMOS transistors 102 and 104. Latch output voltages are indicated as Vout (true) and Vout_(complement) at respective output nodes.
FIG. 2 shows a conventional non-volatile latch structure 200. In this latch, PMOS devices 206 and 208 may be the same or similar to those of the SRAM latch of FIG. 1. However, one or more transistors in this general SRAM structure can be replaced with NVM cells. Here, two N-type NVM cells (e.g., 202 and 204) can be substituted for standard NMOS transistors in order to make the latch non-volatile, such that data can be retained even when chip power is turned off. In other conventional approaches, one of the NMOS transistors may be replaced by an NVM cell, while the other latch leg utilizes an NMOS transistor or a resistor.